/*
 * Copyright (c) Huawei Technologies Co., Ltd. 2018-2023. All rights reserved.
 * Description: SML compute_standard table macro header file
 * Create: 2023/8/18
 */

#ifndef SML_TABLE_DEFINE_COMPUTE_STANDARD_H
#define SML_TABLE_DEFINE_COMPUTE_STANDARD_H

#include "node_id.h"

#define TBL_ID_GLOBAL_SM_NODE                  NODE_ID_SML0
#define TBL_ID_GLOBAL_SM_INST                  1

#define TBL_ID_NIC_RSS_INDIRECT0_SM_NODE       NODE_ID_SML0
#define TBL_ID_NIC_RSS_INDIRECT0_SM_INST       2

#define TBL_ID_NIC_RSS_CONTEXT_SM_NODE         NODE_ID_SML0
#define TBL_ID_NIC_RSS_CONTEXT_SM_INST         3

#define TBL_ID_NIC_VLAN_FILTER_SM_NODE         NODE_ID_SML0
#define TBL_ID_NIC_VLAN_FILTER_SM_INST         4

#define TBL_ID_NIC_FDIR_CFG_SM_NODE            NODE_ID_SML0
#define TBL_ID_NIC_FDIR_CFG_SM_INST            5

#define TBL_ID_OVS_MAC_FILTER_SM_NODE          NODE_ID_SML0
#define TBL_ID_OVS_MAC_FILTER_SM_INST          6

#define TBL_ID_OVS_ETHTYPE_FILTER_SM_NODE      NODE_ID_SML0
#define TBL_ID_OVS_ETHTYPE_FILTER_SM_INST      7

#define TBL_ID_BOND_FWD_SM_NODE                NODE_ID_SML0
#define TBL_ID_BOND_FWD_SM_INST                8

#define TBL_ID_OVS_CAR_SM_NODE                 NODE_ID_SML0
#define TBL_ID_OVS_CAR_SM_INST                 9

#define TBL_ID_OVS_FM_PAIR_CTR_SM_NODE         NODE_ID_SML0
#define TBL_ID_OVS_FM_PAIR_CTR_SM_INST         10

#define TBL_ID_ROCE_DCC_FUNC_SM_NODE           NODE_ID_SML0
#define TBL_ID_ROCE_DCC_FUNC_SM_INST           13

#define TBL_ID_ROCE_RTT_REQUEST_CACHE_SM_NODE  NODE_ID_SML0
#define TBL_ID_ROCE_RTT_REQUEST_CACHE_SM_INST  14

#define TBL_ID_ROCE_CCF_CTR_SM_NODE            NODE_ID_SML0
#define TBL_ID_ROCE_CCF_CTR_SM_INST            15

#define TBL_ID_ROCE_CCF_TOKEN_SM_NODE          NODE_ID_SML0
#define TBL_ID_ROCE_CCF_TOKEN_SM_INST          16

#define TBL_ID_ROCE_LOCK_BHEAP_SM_NODE         NODE_ID_SML0
#define TBL_ID_ROCE_LOCK_BHEAP_SM_INST         17

#define TBL_ID_CAR_SM_NODE                     NODE_ID_SML0
#define TBL_ID_CAR_SM_INST                     18

#define TBL_ID_CTR_DFX_PAIR_SM_NODE            NODE_ID_SML0
#define TBL_ID_CTR_DFX_PAIR_SM_INST            19

#define TBL_ID_BOND_LACPDU_SM_NODE             NODE_ID_SML0
#define TBL_ID_BOND_LACPDU_SM_INST             21

#define TBL_ID_VIRTIO_INTR_BHEAP_SM_NODE       NODE_ID_SML0
#define TBL_ID_VIRTIO_INTR_BHEAP_SM_INST       23

#define TBL_ID_VIRTIO_INTR_AGING_SM_NODE       NODE_ID_SML0
#define TBL_ID_VIRTIO_INTR_AGING_SM_INST       24

#define TBL_ID_PORT_CFG_SM_NODE                NODE_ID_SML1
#define TBL_ID_PORT_CFG_SM_INST                1

#define TBL_ID_NIC_RSS_INDIRECT1_SM_NODE       NODE_ID_SML1
#define TBL_ID_NIC_RSS_INDIRECT1_SM_INST       2

#define TBL_ID_NIC_ELB_SM_NODE                 NODE_ID_SML1
#define TBL_ID_NIC_ELB_SM_INST                 3

#define TBL_ID_NIC_FLEXQ_MAP_SM_NODE           NODE_ID_SML1
#define TBL_ID_NIC_FLEXQ_MAP_SM_INST           4

#define TBL_ID_NIC_VLAN_SM_NODE                NODE_ID_SML1
#define TBL_ID_NIC_VLAN_SM_INST                5

#define TBL_ID_NIC_MULTICAST_SM_NODE           NODE_ID_SML1
#define TBL_ID_NIC_MULTICAST_SM_INST           6

#define TBL_ID_NIC_LRO_AGING_BHEAP1_SM_NODE    NODE_ID_SML1
#define TBL_ID_NIC_LRO_AGING_BHEAP1_SM_INST    7

#define TBL_ID_NIC_LRO_AGING_MISC1_SM_NODE     NODE_ID_SML1
#define TBL_ID_NIC_LRO_AGING_MISC1_SM_INST     8

#define TBL_ID_NIC_LRO_AGING_BHEAP2_SM_NODE    NODE_ID_SML1
#define TBL_ID_NIC_LRO_AGING_BHEAP2_SM_INST    9

#define TBL_ID_NIC_LRO_AGING_MISC2_SM_NODE     NODE_ID_SML1
#define TBL_ID_NIC_LRO_AGING_MISC2_SM_INST     10

#define TBL_ID_OVS_SHARE_PLANE_SM_NODE         NODE_ID_SML1
#define TBL_ID_OVS_SHARE_PLANE_SM_INST         11

#define TBL_ID_OVS_UPCALL_QUEUE_SM_NODE        NODE_ID_SML1
#define TBL_ID_OVS_UPCALL_QUEUE_SM_INST        12

#define TBL_ID_CTR_DFX_OVS_S16_SM_NODE         NODE_ID_SML1
#define TBL_ID_CTR_DFX_OVS_S16_SM_INST         13

#define TBL_ID_ROCE_VFCFG_SM_NODE              NODE_ID_SML1
#define TBL_ID_ROCE_VFCFG_SM_INST              16

#define TBL_ID_ROCE_ONE_WINDOW_SM_NODE         NODE_ID_SML1
#define TBL_ID_ROCE_ONE_WINDOW_SM_INST         17

#define TBL_ID_DFX_LOG_POINTER_SM_NODE         NODE_ID_SML1
#define TBL_ID_DFX_LOG_POINTER_SM_INST         19

#define TBL_ID_CTR_DFX_S64_SM_NODE             NODE_ID_SML1
#define TBL_ID_CTR_DFX_S64_SM_INST             20

#define TBL_ID_CTR_DFX_S32_SM_NODE             NODE_ID_SML1
#define TBL_ID_CTR_DFX_S32_SM_INST             21

#define TBL_ID_CTR_DFX_S16_SM_NODE             NODE_ID_SML1
#define TBL_ID_CTR_DFX_S16_SM_INST             22

#define TBL_ID_OVS_MIRROR_CTR_PAIR_SM_NODE     NODE_ID_SML1
#define TBL_ID_OVS_MIRROR_CTR_PAIR_SM_INST     23

#define TBL_ID_FUNC_CFG_SM_NODE                NODE_ID_SML2
#define TBL_ID_FUNC_CFG_SM_INST                1

#define TBL_ID_NIC_RSS_INDIRECT2_SM_NODE       NODE_ID_SML2
#define TBL_ID_NIC_RSS_INDIRECT2_SM_INST       2

#define TBL_ID_NIC_GLOBAL_QUE_MAP_SM_NODE      NODE_ID_SML2
#define TBL_ID_NIC_GLOBAL_QUE_MAP_SM_INST      3

#define TBL_ID_OVS_CAPTURE_SM_NODE             NODE_ID_SML2
#define TBL_ID_OVS_CAPTURE_SM_INST             4

#define TBL_ID_ROCE_DCC_MCODE_CTX_SM_NODE      NODE_ID_SML2
#define TBL_ID_ROCE_DCC_MCODE_CTX_SM_INST      5

#define TBL_ID_ROCE_PF_PROBE_SM_NODE           NODE_ID_SML2
#define TBL_ID_ROCE_PF_PROBE_SM_INST           6

#define TBL_ID_ROCE_VF_PROBE_SM_NODE           NODE_ID_SML2
#define TBL_ID_ROCE_VF_PROBE_SM_INST           7

#define TBL_ID_ROCE_DIF_TX_BHEAP_SM_NODE       NODE_ID_SML2
#define TBL_ID_ROCE_DIF_TX_BHEAP_SM_INST       8

#define TBL_ID_ROCE_DIF_RX_BHEAP_SM_NODE       NODE_ID_SML2
#define TBL_ID_ROCE_DIF_RX_BHEAP_SM_INST       9

#define TBL_ID_VIRTIO_DB_SUPPRESS_SM_NODE      NODE_ID_SML2
#define TBL_ID_VIRTIO_DB_SUPPRESS_SM_INST      11

#define TBL_ID_OVS_VPCSEC_BHEAP_SM_NODE        NODE_ID_SML2
#define TBL_ID_OVS_VPCSEC_BHEAP_SM_INST        12

#define TBL_ID_OVS_MIRROR_SESSION_SM_NODE      NODE_ID_SML2
#define TBL_ID_OVS_MIRROR_SESSION_SM_INST      13

#define TBL_ID_OVS_VPC_INFO_SM_NODE            NODE_ID_SML2
#define TBL_ID_OVS_VPC_INFO_SM_INST            14

#define TBL_ID_ROCE_IP_HASH_SM_NODE            NODE_ID_SML2
#define TBL_ID_ROCE_IP_HASH_SM_INST            15

#define TBL_ID_NIC_MAC_SM_NODE                 NODE_ID_SML3
#define TBL_ID_NIC_MAC_SM_INST                 1

#define TBL_ID_NIC_RSS_INDIRECT3_SM_NODE       NODE_ID_SML3
#define TBL_ID_NIC_RSS_INDIRECT3_SM_INST       2

#define TBL_ID_OVS_VM_MAPPING_SM_NODE          NODE_ID_SML3
#define TBL_ID_OVS_VM_MAPPING_SM_INST          3

#define TBL_ID_OVS_ETP_SM_NODE                 NODE_ID_SML3
#define TBL_ID_OVS_ETP_SM_INST                 4

#define TBL_ID_OVS_FM_SM_NODE                  NODE_ID_SML3
#define TBL_ID_OVS_FM_SM_INST                  5

#define TBL_ID_OVS_FM_BHEAP_SM_NODE            NODE_ID_SML3
#define TBL_ID_OVS_FM_BHEAP_SM_INST            6

#define TBL_ID_OVS_VPCSEC_KEY_ID_HASH_SM_NODE  NODE_ID_SML3
#define TBL_ID_OVS_VPCSEC_KEY_ID_HASH_SM_INST  7

#define TBL_ID_ROCE_PARAM_SM_NODE              NODE_ID_SML3
#define TBL_ID_ROCE_PARAM_SM_INST              10

#define TBL_ID_ROCE_IP_CTX_SM_NODE             NODE_ID_SML3
#define TBL_ID_ROCE_IP_CTX_SM_INST             11

#define TBL_ID_OVS_XTRACE_SM_NODE              NODE_ID_SML3
#define TBL_ID_OVS_XTRACE_SM_INST              13

#define TBL_ID_MIGRATE_ADDR_SM_NODE            NODE_ID_SML3
#define TBL_ID_MIGRATE_ADDR_SM_INST            14

#define TBL_ID_VIRTIO_DB_BHEAP_SM_NODE         NODE_ID_SML3
#define TBL_ID_VIRTIO_DB_BHEAP_SM_INST         15

#define TBL_ID_VIRTIO_DB_AGING_SM_NODE         NODE_ID_SML3
#define TBL_ID_VIRTIO_DB_AGING_SM_INST         16

#define TBL_ID_CTR_DFX_VIRTIO_S32_SM_NODE      NODE_ID_SML3
#define TBL_ID_CTR_DFX_VIRTIO_S32_SM_INST      17

#define TBL_ID_CTR_DFX_VIRTIO_S16_SM_NODE      NODE_ID_SML3
#define TBL_ID_CTR_DFX_VIRTIO_S16_SM_INST      18

#define TBL_ID_OVS_MIRROR_CAR_SM_NODE          NODE_ID_SML3
#define TBL_ID_OVS_MIRROR_CAR_SM_INST          19

#define TBL_ID_OVS_MIRROR_VTEP_SM_NODE         NODE_ID_SML3
#define TBL_ID_OVS_MIRROR_VTEP_SM_INST         20

#define TBL_ID_OVS_MIRROR_OUT_DIP_SM_NODE      NODE_ID_SML3
#define TBL_ID_OVS_MIRROR_OUT_DIP_SM_INST      21

#define TBL_ID_CRYPT_SAD_BHEAP_SM_NODE                TBL_ID_OVS_VPCSEC_KEY_ID_HASH_SM_NODE
#define TBL_ID_CRYPT_SAD_BHEAP_SM_INST                TBL_ID_OVS_VPCSEC_KEY_ID_HASH_SM_INST

#define TBL_ID_CRYPT_SPD_HASH_SM_NODE                 TBL_ID_OVS_VPCSEC_KEY_ID_HASH_SM_NODE
#define TBL_ID_CRYPT_SPD_HASH_SM_INST                 TBL_ID_OVS_VPCSEC_KEY_ID_HASH_SM_INST

#define TBL_ID_CRYPT_SAD_HASH_SM_NODE                 TBL_ID_OVS_VPCSEC_KEY_ID_HASH_SM_NODE
#define TBL_ID_CRYPT_SAD_HASH_SM_INST                 TBL_ID_OVS_VPCSEC_KEY_ID_HASH_SM_INST

#endif
